Random Stability in Testbench part-2 (Based on UVM)

 Introduction

I already posted what is random stability and why it is required in the testbench. If you want to go through please click here (Random Stability in Testbench part-1). 

UVM itself provides a random stability mechanism. Therefore users need to follow guidelines and make sure provided mechanism don't override. In this blog, I try to cover how UVM random stability mechanism works? what are the drawbacks and how to overcome them? Let's deep dive into UVM based random stability.

Understanding of UVM Random Stability Mechanism.

In typical testbench architecture has two areas where most of the randomization activity is done or the users are generally accepted. 1) uvm_component and 2) uvm_sequence, uvm_sequence_item and uvm_transaction. Both areas have their own mechanism to handle random stability. But both, component and sequence used hash algorithm. So first we understand how the hash algorithm is used fully in terms of achieving stability.

Wherever any component or sequence create then it will register with the factory and make one table with its instance name or full name (consider full path.instance_name). along with that hash algorithm used manual seeding (which was discussed in random stability in testbench part-1). Therefore associated instances name or full name, used srandom() method to get a new seed number. So punch line was one column store full pathname or instance name and other column store associated seed number. To avoid collision used CRC along with the hash algorithm.

//psudo code only

class abc extends uvm_component;

  `uvm_component_utils(abc)

  function new(string name = "abc", uvm_component parent = null);

    super.new(name,parent);

  endfunction //new()

  function void build_phase(uvm_phase phase);

    xyz = XYZ::type_id::create("xyz",this);

    ...

    pqr = PQR::type_id::create("pqr",this);

    ...

  endfunction: build_phase

endclass //abc extends uvm_component

Just an example of a hash table creation using a hash algorithm.

The above table and code represent hash algorithm which contains the full executable instance path and associated seeds. Also, uvm provide a flag for a particular instance whether comes from SystemVerilog's hierarchical seeding mechanism or uvm manual seed generation hashing algorithm by using "use_uvm_seeding".

How does uvm_component achieve Random Stability?

Before going to an internal part of uvm_component, first, we check what the user's requirement was?

Above fig. show the hierarchy of uvm_component. Blue colour shows previously created components/instances and red one shows newly created component/instance. The first thing is what happened if this same scenario run with normal SystemVerilog. "Comp_A" and "Comp_C" gets the same random values as the previous one before "Comp_B" introduce in between. The answer was very straightforward "NO" due to Hierarchical seeding. As a UVM user, we except that if I add a new component "Comp_B" in-between "Comp_A" and "Comp_C" then also previously declared/created component won't be affected (consider random variables).

Solutions

UVM used manual seeding along with an absolute execution path. Therefore in the above example "Comp_A", "Comp_B" and "Comp_C" have individual execution instance paths like top.env.comp_a (same for others as well) and associate seed value using srandom() method. so that all components getting independent seed and RNG of it is distinct with execution instance path. In nutshell, each path contains its own seed and RNG. This all process is done in a hash algorithm and prepared in a table. Also, this mechanism helps to isolate instability within uvm_phase. For example in component "Comp_A" having two $urandom() system tasks and later user added one more $urandom in between than this instability isolated only for that particular run_phase only. Because new components have different paths and seeds so instability components won't affect. Here note that all random system tasks follow SystemVerilog Hierarchical seeding. 

Limitation and its solution.

There are two possible limitations mentioned here. 1)  Thread stability 2) calling randomize() method.

1) Thread Stability

One case where this would happen is shown by the code example below. The value returned by $urandom() is dependent on the thread RNG and since with UVM1.1 and earlier this RNG is not manually seeded prior to the execution of the thread, its state depends on the absolute execution path up to this point. Therefore additional components instantiated during the build_phase() construction phase by this component or elsewhere would influence it, making it unstable. To make this code stable with UVM-1.1 and earlier, just replace $urandom() calls with a call to randomize(). This would make the results depend on the component RNG, and since this one is manually seeded in UVM-1.1, it means that the random value returned would be affected only by other calls to randomize() of the same object.

class abc extends uvm_component;

//…

  task run_phase(uvm_phase phase);

        int unsigned res_delay;

        //…

        res_delay = $urandom_range(0, 20); //or below one used

        randomize(re_delay) with    

        {(res_delay >= 0) && (res_delay <= 20);};

        //…

  endtask

endclass

Making a sure declaration of variables is done in build_phase only. In run_phase() try to used randomize() method for individual variables. avoid using random system tasks as much as possible because it creates instability in the testbench.

2) Calling randomize() method

class comp1 extends uvm_component;

  `uvm_component_utils(comp1)

  rand int a;

  //…

endclass

class env extends uvm_component;

  `uvm_component_utils(env)

  rand int c;   rand int d;

  rand comp1 rand_comp1;

  function void build_phase (uvm_phase phase);        

    assert(randomize(c));

    `uvm_info("env",$sformatf("c = %0h\t d = %0h",c,d),UVM_LOW)

    rand_comp1 = comp1::type_id::create("rand_copm1",this);

    assert(randomize(rand_comp1));             //1

    assert(rand_comp1.randomize());           //2

    `uvm_info("env",$sformatf("rand_comp1.a = %0h",rand_comp1.a),UVM_LOW)

    assert(randomize(d));

  `uvm_info("env",$sformatf("c = %0h\t d = %0h",c,d),UVM_LOW)      

  endfunction

endclass

The green line (comment "1") and the red line (comment "2") may look equivalent, but not from a random stability standpoint. The first call to randomize () selects the object value. In the parent component's RNG, the second call to randomize () selects them based on the RNG of the object itself. The RNG initialization of an object depends on the RNG state of the thread that instantiated the object because the object does not have a unique name and is not set manually at creation time. However, in the UVM1.1a test bench, both methods are stable enough because they are manually seeded before the instantiation function phase is executed. Unfortunately,  this is not the case for UVM 1.1 and earlier versions. Also, the second option reselects the value of the object based on the absolute path of execution.

                                

How do uvm_sequence and sequence_item achieve Random Stability?

Assume a user runs the blue sequence shown in Fig. below, then for some reason modifies it by adding the red sequence item. What the user would expect after running is that TR_A and TR_B remain identical, and a new random sequence item is added between them. This would allow for quicker orientation in the results of the new test and enable accurate finetuning of sequences in order to simulate corner cases. For example, a transaction that fills up a FIFO to a certain level could be added in the middle of an existing sequence to target a specific problematic area. Looking at a slightly more general example in Fig. users would expect that any of the red extensions to the blue sequence hierarchy would not modify the results. Original sequence stimuli should stay the same when new items and sequences are added anywhere in the hierarchy, or when other sequences are started on the sequencer in parallel.

Solution

UVM sequence and sequence_item are created and destroyed multiple times during the simulation. but still, random stability is required in both cases. A change in sequence or sequence_item Hierarchy can't affect existing elements/sequences. So that UVM used the same approach to resolve the stability problem as seen in the uvm_component part. Here sequence and sequence_item are completely isolated from each other and the rest of the testbench by applying manual seeding which is based on their full name. Here used full name instant of the full instance name. because users don't want to generate the same sequence again and ageing and run with same sequencer. there is no meaning to it. If still, users want that it is too stable and possible.

Limitation and its solution.

Here the whole concept of sequence random stability rests on assumption that every sequence and seruqnce_item are uniquely identifiable by their full name. But UVM doesn't force sequences and sequence_item to have a unique name or event name. In absence of unique names, manual seeding becomes meaningless.

For sequence_item there are one provision in uvm that if sequence_item sharing a name would be reseeded based on some sort of counter to differentiate them from each other. To ensure unique naming, it is possible to extend uvm_sequence or uvm_sequence_item classes. So that they check if a name of a top-level sequence and child sequence or item has already been used prior to execution or not.

While using `uvm_do and similar other formats create a problem with reseeding timing. Let's first check below code example.

class sub_sequence extends uvm_sequence #(my_item);

  rand int unsigned num_of_items;

  //…

endclass

class my_sequence extends  uvm_sequence#(my_item);

  sub_sequence sub_seq;

  task body();

    // using create/randomize/start methos

    sub_seq = sub_sequence::type_id::create(“sub_seq”);

    sub_seq.randomize();

    sub_seq.start(get_sequencer(),this);

    //using `uvm_do

    `uvm_do(sub_sequence)

  endtask

 endclass

Both options are about the same, but not in terms of accidental stability. The `uvm_do macro manually seeds the sequence before it is randomized, while the create/randomize/start methods manually seed it only after randomization. This means, for example, if you use to create/randomize/start as above if you do additional instantiations in the body() task of the parent sequence, the marginal fields of the subsequence (that is,  num_of_items in the above example). This means that will change. Note that this  only applies to uvm_sequences  executed by start (), not  uvm_sequence_items  executed by start_item()/finish_item ().

Since using `uvm_do macros should, in general, be avoided we recommend that users simply reseed sequences by themselves before they are randomized. Also, it should be noted that `uvm_do derivatives can`t create the top-level sequences, which must always be executed using start(). Therefore using them would solve the problem only partially. The code below shows how to use the preferred create/randomize/start method so that manual seeding takes place before randomization. The solution is to insert a call to set_item_context() before randomization. This function initializes the sequencer and parent sequence fields of the subsequence, allowing full name computation and reseeding.

class my_sequence extends uvm_sequence#(my_item);

  sub_sequence sub_seq;

  task body();

    // using create/randomize/start

    sub_seq = sub_sequence::type_id::create(“sub_seq”);

    sub_seq.set_item_context(this, get_sequencer());

    sub_seq.randomize();

    sub_seq.start(get_sequencer(),this);

endtask

endclass

Click Here for detail example.

Conclusion

A randomly stable testbench is required. No matter how a user would achieve. The best way to achieve random stability is locking a seed to that particular thread. If a user can do that for the entire simulation that easily we can say that that testbench was randomly stable.

Reference 

[1]  IEEE Standard for System Verilog- Unified Hardware, Design, Specification and Verification Language”, IEEE std 1800-2009, 2009.

[2]  UVM 1.1a Reference, www.uvmworld.org 

[3] “Are OVM & UVM Macros Evil? A Cost-Benefit Analysis”, Erickson, Adam, 2011

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