Verification Deep Dive

  Introduction I already posted what is random stability and why it is required in the testbench. If you want to go through please click here  (Random Stability in Testbench part-1).  UVM itself provides a random stability mechanism. Therefore users need to follow guidelines and make sure provided mechanism don't override. In this blog, I try to cover how UVM random stability mechanism works? what are the drawbacks and how to overcome them? Let's deep dive into UVM based random stability. Understanding of UVM Random Stability Mechanism. In typical testbench architecture has two areas where most of the randomization activity is done or the users are generally accepted. 1) uvm_component and 2) uvm_sequence, uvm_sequence_item and uvm_transaction. Both areas have their own mechanism to handle random stability. But both, component and sequence used hash algorithm. So first we understand how the hash algorithm is used fully in terms of achieving stability. Wherever any componen...

Introduction        Over the past few years, random verification has proven itself to be very effective in rapidly uncovering or unexplored design bugs. So the quality of the random stimulus or testbench is very important in order to achieve a high degree of confidence that a design has been well tested and bug-free. But using random constrain verification there is potential that the test case may become reproducible due to certain changes in testbench during the development cycle.  In this article, I try to cover why random stability is required for any testbench and its consciousness and significance. Also cover what are the solutions to achieve random stability for SystemVerilog and UVM. Required understanding of Random Number Generator (RNG)     Before understanding random stability we need to understand How to declare or initiated variables to get a random value. All EDA developers have their own RNG. Therefore when the same code run in a differen...