All About UVM Reporting
What we have in Verilog and SystemVerilog for Reporting. Verilog and SystemVerilog have some system tasks for reporting and displaying messages. We all used $display, $error, $info, $monitor, $write, $fatal, $strobe and whatnot for different purpose like display data or messages, display errors, formatted messages and etc. Without going into detail, quickly recap these system tasks. $display: Printing a formatted and non-formatted message in the console. Automatically add a new line at end of the message. $info: Indicated assertion fail or not. It prints messages with additional information like time, path, line no and etc. $warning: It provides a run-time warning and is suppressed by a tool. $error: It provides a run-time error message. $fatal: It provides run-time fatal error and terminated simulation when it encounters. $monitor: Keep tracing variables and printing them...