Verification Deep Dive

What is interrupt?  The interrupts are signaled through which some unusual or special events acknowledge to users.  Interrupts are either hardware or software or both generated. Sometimes system generates interrupts or the user also can generate interrupts, it totally depends on system design and its use case. Software interrupts usually used register to acknowledge and hardware interrupts used direct signals to acknowledge. In nutshell, interrupts are events that can be triggered parallel threads of processes. Importance of Interrupts For any SoC level or system-level where multiple blocks work together, prepare complex design, in that case, all components work together and are compatible with each other that's why to introduce some exceptions and acknowledge of it, its call interrupts. Sometimes SoC Design used a separate Interrupt controller to handle such requests. So interrupt controller helps to manage system or subsystem level interrupts via enabling and disabling inter...

     What we have in Verilog and SystemVerilog for Reporting.           Verilog and SystemVerilog have some system tasks for reporting and displaying messages. We all used $display, $error, $info, $monitor, $write, $fatal, $strobe and whatnot for different purpose like display data or messages, display errors, formatted messages and etc. Without going into detail, quickly recap these system tasks. $display:   Printing a formatted and non-formatted message in the console. Automatically add a new line at end of the message. $info:   Indicated assertion fail or not. It prints messages with additional information like time, path, line no and etc. $warning:  It provides a run-time warning and is suppressed by a tool. $error:  It provides a run-time error message. $fatal:  It provides run-time fatal error and terminated simulation when it encounters.    $monitor:  Keep tracing variables and printing them...